Altera announces OpenCL Program for FPGAs

VARINDIA- INDIA'S FRONTLINE IT MAGAZINE

Altera Corporation has announced a development program focused on the Open Computing Language (OpenCL) standard for FPGAs and SoC FPGAs. The OpenCL standard is a C-based open standard for parallel programming. Altera's OpenCL program combines the parallel performance capability of FPGAs with the OpenCL standard to enable powerful system acceleration. This heterogeneous system (CPU plus FPGA using the OpenCL standard) also has a significant time-to-market advantage compared to traditional FPGA development using lower level hardware description languages (HDLs) such as Verilog or VHDL.

Through its OpenCL program, Altera has engaged with multiple customers and expanded its university program to support the OpenCL standard for FPGA development in academia, and is actively contributing to the evolution of the OpenCL standard based on customer feedback. Early results of customer evaluations show a 35X performance increase compared to multicore CPU solutions, and a 50 percent reduction in development time compared to HDL-developed FPGA solutions.

Udi Landen, VP, Software and IP engineering, Altera said, "The OpenCL standard enables designers to accelerate their designs and improve their productivity by taking advantage of parallel architectures within the C programming environment. We have been actively engaged in OpenCL development for years, and are now collaborating with the industry consortium, customers' system architects, and academia to drive FPGA support in the OpenCL standard."

The OpenCL standard offers a natural separation between "host" code-pure software, written in standard C/C++, that can be executed on any type of microprocessor-and the "kernel" code, written in OpenCL C, that runs on the accelerator. By profiling their algorithms, system architects can choose which functions to accelerate as kernels in the FPGA device to improve system performance. Multiple kernels can operate in parallel to further speed up processing. The host communicates with the accelerator device via a set of library routines with a minimal set of extensions that allow programmers to specify parallelism and memory hierarchy for the most computationally intensive portions of the code.


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